[XviD-devel] Cacheline, portab.h

[Christoph Lampert]

Hi,

I'm still not finished complaining about portab.h. Sorry for that ;-)

What do we do with CACHE_LINE argument from portab.h ? Just alignment of
matrices? I didn't find any prefetch-code based on this (would be a good
idea, too, btw.) 

I was just asking because if it's were really important, we should not use
a fixed definition based on architecture 

#if defined(ARCH_IS_32BIT)
#    define CACHE_LINE  16
#elif defined(ARCH_IS_64BIT)
#    define CACHE_LINE  32
#endif

(if this is bytes, it's rather wrong, btw, since imho most 32bit CPUs
have 32 (PII/PIII/PowerPC) or even 64 bytes (P4,Athlon) cachelines ) 

On x86 we could get this using configure directly from CPUID, as
"cpuid" does:  http://freshmeat.net/projects/cpuid/?topic_id=146
For crosscompiling or on other plattforms, it could also be predefined,
but adjustable during configure. 

gruel 

--------- typical output of cpuid.c (which claims to be GPLed) ---------

 eax in    eax      ebx      ecx      edx
00000000 00000002 756e6547 6c65746e 49656e69
00000001 00000683 00000002 00000000 0383f9ff
00000002 03020101 00000000 00000000 0c040882

Vendor ID: "GenuineIntel"; CPUID level 2

Intel-specific functions:
Version 00000683:
Type 0 - Original OEM
Family 6 - Pentium Pro
Model 8 - Pentium III/Pentium III Xeon - internal L2 cache
Stepping 3
Reserved 0

Brand index: 2 [Pentium III processor]

Feature flags 0383f9ff:
FPU    Floating Point Unit
VME    Virtual 8086 Mode Enhancements
DE     Debugging Extensions
PSE    Page Size Extensions
TSC    Time Stamp Counter
MSR    Model Specific Registers
PAE    Physical Address Extension
MCE    Machine Check Exception
CX8    COMPXCHG8B Instruction
SEP    Fast System Call
MTRR   Memory Type Range Registers
PGE    PTE Global Flag
MCA    Machine Check Architecture
CMOV   Conditional Move and Compare Instructions
FGPAT  Page Attribute Table
PSE-36 36-bit Page Size Extension
MMX    MMX instruction set
FXSR   Fast FP/MMX Streaming SIMD Extensions save/restore
SSE    Streaming SIMD Extensions instruction set

TLB and cache info:
01: Instruction TLB: 4KB pages, 4-way set assoc, 32 entries
02: Instruction TLB: 4MB pages, 4-way set assoc, 2 entries
03: Data TLB: 4KB pages, 4-way set assoc, 64 entries
82: 2nd-level cache: 256KB, 8-way set assoc, 32 byte line size
08: 1st-level instruction cache: 16KB, 4-way set assoc, 32 byte line size
04: Data TLB: 4MB pages, 4-way set assoc, 8 entries
0c: 1st-level data cache: 16KB, 4-way set assoc, 32 byte line size